Description:
StateCAD - State Machine Editor

StateCAD can help take complex state machine design from concept through synthesis in minutes. StateCAD accelerates design entry by allowing quick entry of finite state machines (FSMs). Each step is automated, reducing development costs and enhancing effectiveness.

StateCAD allows users to quickly design FSMs, find and fix design errors, verify behavior, and generate optimized HDL. StateCAD automatically analyzes designs for problems such as stuck-in-states, conflicting state assignments, and indeterminate conditions. This automated error analysis insures that designs are logically consistent, reducing simulation requirements and improving product reliability.

StateCAD is included in ISE Foundation, ISE Alliance, ISE BaseX, and ISE WebPACK.

Introduction
StateCAD is a graphical entry tool that allows engineers to express their ideas in a natural manner, as state diagrams. This allows for designs without cumbersome, text oriented and error prone rules. Hardware designers can now capture their ideas without the use of handwritten documentation which quickly becomes outdated.

StateCAD has been designed for simplicity in use as a tool for digital design, documentation, and error analysis. StateCAD include StateBench (test bench generation and behavioral verification), Wizards (FSM, Logic, Design, Optimization), the HDL Browser, and 32 bit compliance.

After validating a diagram, StateCAD automatically generates simulatable and synthesizable HDL code directly from the diagram. The HDL is valid, consistent, maintainable, and accurately implements the graphical diagram. The HDL can be VHDL, Verilog, or Abel the language may be changed at the click of a button. StateCAD enhances productivity, reduces product development cost, and accelerates time to market.

Interactive dialog boxes provide the designer with a way to discover unused conditions, stuck at states, indeterminate conditions, syntax errors and incomplete portions of state diagrams early in the design cycle. StateCAD allows the designer to find bugs prior to simulation, saving engineering time, computer resources, and improving product reliability.

Once a design is completed in StateCAD, it may be verified within StateBench. After verification, a timing constrained test bench can be written automatically. The test bench can be used for post synthesis timing verification.

The Process Flow
StateCAD is used as the front end tool for developing state diagrams and initial design analysis. The outputs of StateCAD are language specific code files (VHDL, Verilog or Abel) and professional documentation. StateCAD supports the most popular HDLs and provides vendor specific support for VHDL and Verilog, to insure tool compatibility and optimal synthesis results.

Once a design has been implemented in StateCAD, the behavior should be verified using StateBench. StateBench allows you to step through the state machines and make sure your design functions as intended. Automatic behavioral verification speeds the testing process, and once a design has been verified, you can have StateBench write out a timing constrained VHDL (or Verilog) for post synthesis timing verification!