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Location: Main > Design > Verilog and VHDL Tools
| Accolade Design Automation -- VHDL design, simulation and synthesis tools. |
| Aldec -- HDL design entry and simulation software for programmable logic designers. |
| C Level Design -- Offers a design and verification environment for C/C++ with synthesis to VHDL and Verilog code. |
| Calyptech Design Services -- Offers ASIC and FPGA design and verification services, drivers and tools. Includes product and service overview and PDF detailed product specifications available. |
| CAST, Inc. -- Tools for intellectual property (IP) management. Plus synthesizable cores and simulation models using VHDL and Verilog. |
| Cypress Warp Tools -- VHDL and Verilog tools for use with the Cypress CPLD family. |
| Doulus -- Lots of VHDL and Verilog resources. Including PaceMaker Self-Teach software. |
| Esperan -- VHDL, Verilog and FPGA training courses held in the US, Europe and the UK. |
| Exemplar Logic, Inc. -- Provides LeonardoSpectrum which is a CPLD, FPGA and desktop ASIC synthesis solution. |
| Experimental Computing Laboratory -- Includes papers, presentations, conference publications and SAVANT VHDL, a free VHDL analyser and simulator. From University of Cincinnati. |
| eXsultation -- Specialize in full turn-key, customer facility training programs in VHDL, Verilog,C++ modeling, formal verification, and FPGA design. |
| Freeware Verilog & VHDL -- This is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project, still in its infancy). |
| Green Mountain -- VHDL compilers and design environments, including Windows, DOS and Linux support. |
| iMODL -- The iValidate toolset comprises ready-to-use functional verification tools and simulation models. |
| Nova Engineering -- Megafunctions are modular, DSP algorithms and functional blocks for custom use in PLD or ASIC designs. |
| Rajesh Verilog FAQ -- General Verilog resource that includes a FAQ, tutorials, and commercial information. |
| Sandstrom Engineering -- HDL pre-synthesis tools which check code for synthesizability. Then suggest replacement code where problems are found. |
| Saros -- Offering a full suite of VHDL and Verilog design tools, from design-entry, simulation and synthesis to verification and training. |
| StateCAD -- Automatic VHDL and Verilog code from graphical state machine and data flow logic. |
| Sutherland HDL, Inc. -- Provides Verilog HDL and Verilog PLI training workshops and consulting services. |
| Symphony EDA -- VHDL Simili a freeware VHDL compiler/simulator. It supports VHDL"93, Vital, and SDF. Support for Altera, Atmel, Cypress and Xilinx. |
| SynaptiCAD -- Provides Verilog, VHDL, TDML, logic analyzer, pattern generator, and SPICE tools. |
| Synplicity -- Logic synthesis and verification products for FPGA and ASIC designers. |
| The Hamburg VHDL Archive -- A collection of public-domain or shareware, VHDL documentation, models, and tools. |
| Time Rover -- Provides tools for aiding Verilog development. Including The Temporal Rover for automatic verification of protocols and Verilog Java PLI. |
| TimingTool - Online timing diagram editor -- Free to use online timing diagram editor. Timing diagrams are saved in TDML format. Translators from TDML to DXF, VHDL, and Verilog are also supplied. |
| Translogic -- EASE and EALE provide HDL aware entry tools, both graphical and text based. Also providing Linux support. |
| Verilog Dot Com -- Verilog resources page. Includes FAQ, books and links. Also verilog aware Emacs add on. |
| Verilog-AMS -- The Verilog-AMS Technical Subcommittee has been created with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. |
| VHDL FAQ -- General VHDL resource including and information on books, tutorials, commercial products, and a FAQ. |
| VIZEF -- Provide graphical HDL tools for design and verification. |
9145 Ranier
Minneapolis MN 55311 USA
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