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OCP-IP Announces Availability of Mentor Graphics CheckerWare Library of Verification IP

PORTLAND, Ore.--(BUSINESS WIRE)--May 10, 2005--Open Core Protocol International Partnership (OCP-IP) today announced that the OCP interface is the latest addition to the Mentor Graphics(R) CheckerWare(R) library of verification IP. The CheckerWare solution is comprised of a library exceeding 100 assertion checkers and protocol monitors, making possible the quick adoption of cutting edge assertion-based and formal verification methodologies without the cost and risk often associated with the adoption of new tools. The monitor currently supports OCP v2.1, the organization's newest standard, announced in March. OCP 2.1 includes profiles for the most commonly coupled OCP features and an advanced tagging scheme for enhancements in out-of-order processing.

The CheckerWare monitor is an advanced verification technology that can be used to verify OCP during simulation and formal functional verification. Additionally, the monitor collects detailed coverage information, such as protocol interface behaviors of industry standard interfaces, to identify coverage weaknesses in the user's verification scheme. CheckerWare components are added to the designs and used throughout the verification flow. This in turn facilitates faster, more complete verification, and ensures that devices fully comply with the OCP specification.

"OCP has a robust, thriving infrastructure supported by many independent companies such as Mentor that provide excellent services and products," said Ian Mackintosh, president OCP-IP. "This is a testament to the tremendous adoption we have seen throughout the industry."

"Mentor Graphics is proud of being a contributor to the OCP-IP organization, with OCP as a leading interconnect to our customers designing complex SoCs," stated Steve White, general manager of Mentor Graphics' 0-In Functional Verification business unit, which provided the CheckerWare library. "The addition of the CheckerWare OCP monitor enables these customers to quickly adopt the advanced methodologies needed to reach verification closure."

About OCP-IP

The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants are: Nokia (NYSE:NOK), Texas Instruments (NYSE:TXN), ST Microelectronics (NYSE:STM), Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics.

OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. VSIA endorses the OCP socket, and OCP-IP is affiliated with the VSI Alliance. For additional background and membership information, visit www.OCPIP.org.

Contacts


OCP-IP
Ian Mackintosh, 650-938-2500 ext. 106
ian@ocpip.org
or
VitalCom
Joe Basques, 650-366-8212 ext. 202
joe@vitalcompr.com

Zuken claims 3-D routing checker cuts design time up to 6 weeks

06 Jun 2005 - Zuken has introduced a two- and three-dimensional routing checker for high-voltage PCBs that the company claims cuts typical design time by six weeks.

According to Zuken, the Spacing Synthesizer tool allows designers to check for adequate separation of signal paths in the Z dimension of a PCB in a matter of minutes. By contrast, the company said, Z-axis checks are traditionally done manually and can take designers up to six weeks on a typical four-layer board.

Spacing Synthesizer enables engineers to assign groups of signals, and the distance between signals of the same or a different group, from within the system schematic during the design process. The signal groups can then be visualized in different colors within System Designer, the schematic capture module of Zuken's CR-5000 enterprise-wide PCB design suite. A distance-matrix is automatically created that shows the design rules required in Board Designer, the tool-suite's board layout module.

Automating the design rule checking process reduces human error and assures board integrity with respect to conductor spacing, Zuken said. Spacing Synthesizer's 3-D check is also adjustable for varying board thicknesses and design rule exceptions, Zuken said, allowing variations in board fabrication process to be considered.

The Spacing Synthesizer tool works within CR-5000. The Spacing Synthesizer complete package, which includes front-end base spacing rule definition, back-end design rule stack generation and full 3-D design rule check is available now and is priced from $58,500. More information about the tool is available at Zuken's website.

- Dylan McGrath
EE Times

Gartner and Global Sources Release Annual Study on EDA in China and Taiwan

Gartner, Inc. - October 11, 2004

Global Sources Ltd. and Gartner, Inc. published results of their fourth annual joint study, "Design Trends and Electronic Design Automation Tools: Mainland China and Taiwan." The study indicates growing use of finer process technologies in the design of standard Integrated Circuits and Application-Specific ICs in mainland China and Taiwan.

Finer process technologies enable the production of highly integrated, compact components, which can then be used to make smaller, more efficient electronic devices. The survey shows while 0.35 microns remains the mainstream technology for standard ICs in Taiwan, 27 percent of Taiwan respondents already engage in 0.18-micron designs. In mainland China, 33 percent of respondents design at 0.18 microns.
In ASIC design, 0.18 microns has also become more prevalent, with 35 percent of mainland respondents and 49.5 percent of Taiwan respondents working with 0.18-micron designs.

Consumer electronics, communications lead applications

The joint study highlights the importance of consumer electronics applications for Taiwan designs, with 32 percent of Taiwan respondents citing it as the segment where their designs are most often used. Communications came second, at 19 percent; and computers and computer peripherals was third, at 18 percent.

"This finding demonstrates the shift in focus among Taiwan engineers that we first saw in the 2003 Design Trends & EDA Tools: Mainland China & Taiwan survey. In 2002, most Taiwan respondents considered computers their primary application segment,'' said EE Times-Asia publisher, Mark A. Saunderson.

In mainland China, communications applications dominate design, a result similar to that of last year. Nearly 29 percent of survey respondents cited communications as their primary area of application, followed by industrial, instruments and medical applications at 21 percent, and consumer electronics at 19 percent.

Engineers use range of EDA tools

Surveyed designers rely on a number of EDA tools in their work. The most popular tools among mainland China respondents are those used for PCB layout (used by 66 percent of respondents); logic synthesis (39 percent); and timing analysis (37 percent). In Taiwan, the top tool category is also PCB layout, used by 49 percent of respondents, followed by analog simulation at 41 percent; and logic synthesis at 38 percent.

''Our 2004 updated forecast indicates that the EDA software and software maintenance market will achieve revenues of $4.192 billion this year, an increase of 7.4 percent from $3.903 billion in 2003," said Nancy Wu, an analyst at Gartner Dataquest's design and engineering group. "The market is expected to grow at a 12.5 percent compound annual growth rate (CAGR) to reach $7.025 billion in 2008. And Asia-Pacific will outpace other regions with a 17 percent CAGR through 2008.''

The joint research also compared design-to-prototype lead times, gate counts, number of design iterations and other key parameters of electronics design.

About the study

Design Trends & EDA Tools: Mainland China & Taiwan presents findings from an online survey of 607 mainland China engineers and 321 Taiwan-based engineers. It identifies and compares trends in electronic design and in the use of EDA tools in mainland China and Taiwan. The research is the fourth such joint initiative by Global Sources' biweekly design publication, Electronic Engineering Times-Asia (EE Times-Asia) and Gartner. Visit EE Times-Asia online to register for and access a more detailed analysis of the results.

Source: Xinhua-PRNewswire-FirstCall.

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