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New Challenges in Design

By Ed Sperling -- Electronic News, 2/11/2005

Electronic News sat down to discuss the need for co-designing hardware and packaging with C.Y Ho, VP of R&D engineering at Synopsys; Andrew Yang, chairman and CEO of Apache Design Solutions; Steffen Rochel, engineering group director for DFM electrical verification at Cadence Design Systems; and Jiayuan Fang, president of Sigrity. What follows are excerpts of that discussion.

Electronic News: Let’s start out with a general question of how your individual companies get involved in co-design and what the overriding problem is.

Ho: We’ve been working since the Avant! acquisition by Synopsys to bridge the packaging and tool design together because we see it as a great growth market.

Yang: We’ve primarily focused on power, including dynamic power integrity. Instead of IC package co-design, we call it global design for dealing with simultaneous switching noise. It is the symptom of simultaneous switching output, or SSO. That manifests itself as ground bumps, which can promulgate from the source into the core and impact the timing and chip performance. Obviously it has a lot to do with the package. Global means on-chip, power managed networks, which include I/Os and drivers, and then you have package and PCBs. You cannot just look at sections or five I/Os. You have to look at hundreds, because the number of pins is increasing going down to 90 nanometers.

Rochel: Because of the need of the customer, we are extending collaboration across Cadence to work with packaging tools and IC implementation tools, and trying to bridge the gap between the package design from an early design down to issues related to simultaneous switching noise, timing and signal integrity. We are trying to provide a solution that includes not only complete design flow, but also a flow that bridges the gap between package and PCB on one side, and IC design on the other.

Fang: We’re focused on signal integrity and power integrity. Our main product emphasis in the past has been in electronic packaging and boards, analyzing high-speed systems for power integrity and simultaneous switching noise. We are getting into co-design primarily because our customers are telling us that to do the power system well you have to use co-design. The IC and the package are not separate. Previously we were working on co-design of packages and boards. Two years ago we began looking at co-design of ICs and packages and found there are significant deficiencies.

Electronic News: Co-design hasn’t always been a topic of conversation in this industry. At what process node did co-design become vital?

Ho: At the core side, a lot of issues started at 90 nanometers. Because there is much lower voltages and low power needs and multiple voltages, the noise margin became lower. That means you need better power management. From the packaging side, the need started with a flip chip, which has a lot of pins. The complexity is beyond the normal design, so you need a co-designed system to manage the complexity. You need to manage the bump location and package pin or core pins so the redistribution layer is routable. That’s a first step. Once that’s done, you start talking about power integrity and electrical analysis.

Rochel: The problem is solved at 130 nanometers. At 90 nanometers, it becomes critical for the ASIC or SoC market, or down the road for [system in package]. You’re looking at dependencies between the core chip design and package, but also the interface between the chip, package and board.

Electronic News: So what we’re really talking about here is system-level design. Is that correct?

Rochel: If you look at it purely from a power perspective, if you design a PCB you have to understand what noise will be generated by the power supply at the PCB and how the power planes will be designed to drive the power into the package and into the chip. That allows you to follow through what noise will look like from the outside, and vice versa. From the IC perspective, you need to know what noise is generated on the IC, how it gets modified or impacted through the package, what kinds of tradeoffs you can make between on-chip optimization versus package optimization to minimize noise, and then how is the noise impacting the different chips on a PCB. That’s just from a power perspective. The same is true from a signal integrity perspective.

Yang: The best way to understand is to walk through an example from a major system design company. They already have in place a packaging modeling tool and all the sophisticated IC design tools. Last year, they began having chip failures. One reason is the number of I/Os is going above 500. The amount of noise, or simultaneous switching current, is rising above 500 millivolts. The noise margin is becoming smaller as we move to new processing nodes.

Electronic News: Isn’t that partly a function of less physical room on smaller chips?

Yang: Yes. The power density is higher and there is less protection you can put in. You have to analyze in a global sense. The failure actually comes from the timing, but the noise is the source of the failure in timing. The problem is not just linear. You have a source coming out from simultaneous switching, and the noise carries itself through the medium and through the non-linear effect of the transistor. That causes the timing to fail. The number of I/Os is increasing. The frequency is increasing, so you have high-speed I/O going up a gigahertz. The effects that were not important are now becoming important. It’s all working against you as you go down to 90 nanometers and 65 nanometers.

Fang: Before this, you might not have needed co-design. The reason is the IC design and the package could be separate, and they were not that interdependent. With a flip chip, the connection between the IC and the packages are closely related. There are two areas where you need co-design. One is power. You have to co-design them together because there are so many connections that interact at different times. Another place is simultaneous switching noise, the I/Os. The power system noise is global, so you have to have a global power systems model with the I/O. The package model is no longer simple. The tools now only do ICs. They don’t take into account all the interactions.

Electronic News: What happens now that we have more and more functions built into a chip, such as a cell phone that’s also an MP3 player, a camera and a game console?

Yang: The more devices you pack in, and the more you deal how many switches are on and how many are off, the more you have to deal with simultaneous current spikes, which are basically the source of the noise. Noise is propagated through a passive network medium and manifests itself in timing delay glitches. From an IC developer’s point of view, a package model is always a model. It may be inaccurate or oversimplified, but it is still a model. You can extend that, but a designer looks at it as data. Co-design means the generation, first, of an accurate system model. Second, you need to take the model as data into the IC design domain. From a designer’s point of view, they don’t want to deal with the creation of the model. They want to focus on implementation and making sure the timing meets the design budget.

Rochel: While I agree with you, I would also extend the meaning of co-design. What you refer to is analysis verification once the design is done. But if you look at the problems system design houses are facing, it’s a question of finding the optimum solution between chip and package. How do you optimize the location of the I/O pads or the power bumps? What modification do you need to do on the package or IC sides to achieve an optimum solution? One example is, where do you put power ground decoupling cups? Should it be off the package, in the package or on the chip? And depending on the choices, you achieve a completely different system behavior. It’s not only the electrical generation. It’s also a question of how you bridge the gap between the package domain and the IC implementation domain to achieve an efficient data flow and achieve an efficient ECO loop.

Yang: You brought up a good point. There is a difference between IC and package co-design and IC and package co-verification and co-analysis. They are purposely different. You cannot get an accurate analysis into the design phase because the amount of data is too huge. From the standpoint of design, how do you generate a model that can be used for IC implementation? Second, how do you generate a power model to be used for the system package design to meet the power budget? The design issue involves creation of a simplified model to be used for each domain.

Ho: Those models need to be consistent. Separating them is for sign-off purposes, but for implementation or design you need to have a quick visibility check such that you create a model to analyze that. But you need to extend that and figure out what you want to do that analysis for. Where is the location you want to put in, how large is the package, and what should power management look like to solve the I/O problem all together. Once you start, you need a more accurate model. But all of those need to be part of the system.

Rochel: But if you look at where design teams are struggling today, it’s as simple as the data exchange between the IC implementation, the place-and-route tool and the package design tool, and also to enable a data flow going back and forth.

Ho: You need to pool the data so you are not back and forth between the packaging group and IC designers.

Yang: The IC designer does not want to learn SPICE, but I/Os have to be represented as a SPICE model. If they don’t want to deal with that, what makes you think they want to deal with finite different time domain methods and full wave solutions for the package? This is way beyond the knowledge base. You want the IC designer focused on designing a chip in the shortest amount of time. That’s why the model from the package has to be accurate. But the designer needs to be able to take those tools and easily connect them into their system. The connection part is where we’re suffering today.

Fang: The main objective is to have a technology and path on tools, which take into account interactions between ICs and packages. You can separate the ICs and packages to generate package models and then do the IC. That’s one way. You can put the IC and package together and do a co-simulation and co-design. That’s another way. In various applications, you need simplification at different levels. For example, in the board design, you don’t need the entire chip to model it. For system levels, you need to find the right approximations at the right places. If we cannot do these simple separations, we need to find other ways to do it.

Electronic News: Does this whole process get more complicated with a system on a chip using intellectual property from multiple vendors?

Ho: This is part of the overall trend toward density. Now at 90 nanometers you can put more into the chip, and most of this will be in consumer products. The main requirement is power management. How do you get the power to go through the center of the core? The first need we see is the peripheral I/O. There’s a power bump in the center. You have to make a connection from the outside to the center of the core. That’s one side of the flip chip problem. But if you have more I/O, you need more I/O area in the center of the core. That becomes a more severe core design issue because it’s no longer a [simultaneous switching output] in the peripheral. In the past, the designer tried to do an I/O power rail so that the I/O noise wouldn’t affect the core noise. In the center of the area, there’s more noise. It becomes difficult to manage from a power density and a noise point of view.

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